stdlib / store

✓ 15 passing ○ 6 planned

Lessons

1 ✓ Passing
001 store create stored watch
2 ✓ Passing
002 store watch guard producer if
3 ✓ Passing
003 store interceptor cross store sync
4 ✓ Passing
004 store no torn state
5 ✓ Passing
005 store plural query watch
6 ✓ Passing
006 store reject watch body ambient context
7 ✓ Passing
007 store reject take leak
8 ✓ Passing
008 store update where
9 ✓ Passing
009 store chain envelope multi write
10 ✓ Passing
010 store multi watch same field
11 ✓ Passing
011 store insert capacity full branch
12 ✓ Passing
012 store reject cascade cycle
13 ✓ Passing
013 store cross store guard closure
14 ✓ Passing
014 store stripe scan firing
15 ○ Planned
015 store take give back disposal — IDEA PIN — DESIGN-GATED, not machinery-gated (2026-07-05 sweep): the
16 ○ Planned
016 store lifecycle inserted removed — IDEA PIN (ruling 5, rung two) — BLOCKED on TWO opens (2026-07-05
17 ○ Planned
017 store backend arms di — IDEA PIN (T8) — DESIGN-GATED (2026-07-05 sweep): `! ?persist`
18 ○ Planned
018 store declared key addressing — IDEA PIN (O2 head 3) — WALLED on infra (2026-07-05 sweep): key
19 ○ Planned
019 store batch insert fused cascade — IDEA PIN (residue-tier, no spelling yet): batch insert + full cascade fusion — T2's acyclic comptime cascade DAG topo-sorted and fused into one straight-line body per write site, batches applied column-wise over SoA (SIMD), batch = the transaction envelope. See residue.md.
20 ○ Planned
020 store compound field types — IDEA PIN (residue-tier, no spelling yet): compound store field types — f32/f64 scalar columns, vec3, mat4x4. Prerequisite for every one-to-one ecs-store benchmark entry; kernel:shape's green f64 fields (390_001) prove the transform substrate already handles float columns — rung one's non-i64 wall is scoping, not architecture. See residue.md.
21 ✓ Passing
021 store f64 scalar columns